Consider a system with 36-bit virtual addresses, 32-bit physical addresses, and 4KB pages.

Question

Consider a system with 36-bit virtual addresses, 32-bit physical addresses, and 4KB pages. The system uses a page table to translate virtual addresses to physical addresses; each page table entry includes dirty (D) and resident (R) bits.

a) Assuming a flat page table, what is the size of each page table entry, and how many entries does the page table have?

Translation Lookaside Buffer(TLB)

Virtual Page Number(VPN) Tag	Valid Bit(V)	Dirty Bit(D)	PPN(Physical Page Number) in HEX
00000A	0	0	0A521
000016	1	0	7390E
000009	0	0	1230A
000001	1	0	12300
000023	1	1	A390E
000007	1	1	A1215
00001C	0	0	0001C

00000E

1

1

756AC

Page Table

Virtual Page Number(VPN) in HEX	Resident Bit(R)	Dirty Bit(D)	PPN(Physical Page Number) in HEX
0	0	0	—
1	1	0	12300
2	0	0
3	1	1	23A21
4	0	0
5	1	0	9812A
6	1	1	50200
7	1	1	A1215
8	0	0

9	0	0
A	1	0	0A521
B	1	0	B2178
C	0	0
D	0	0
E	1	1	756AC
F	0	0
10	1	0	3141F
11	1	0	5171B
12	1	0	6721A

13	1	1	0A0BC
14	1	1	100AB
15	1	1	80AB1
16	1	0	7390E

Each logical address is initially verified to see if it exists in the TLB.

Fill in the Table below

Virtual Address(VA) in HEX	TLB Miss? (Y/N)	Page Fault? (Y/N)	PPN(Physical Page Number) in HEX	PA(Physical Address) in HEX
00000E
000016
000007
00000A
000011
00000C
000001
000009
000010

000003

Summary

It’s a TLB miss if it’s not present, thus it’s checked in main memory.

The resident bit is tested if it is present in the main memory.

If the resident bit is set, the page address is calculated by adding the page number offset to the page address.

It causes a page fault if its resident bit is not present.

A valid bit is tested if it is present in the TLB. It is a TLB hit if the valid bit is set. Otherwise, TLB will be skipped and must be examined in the main memory.

If the dirty bit is set in the TLB, the main memory must also be updated.

Explanation

 

VA (Virtual Address in HEX)	TLB Miss? (Y/N)	Page fault? (Y/N)	PPN (Physical Page Number) in HEX	PA (Physical Address) in HEX
00000E	N	N	756AC	756ACE
000016	N	N	7390E	7390E16
000007	N	N	A1215	A12157
00000A	Y	N	0A521	0A521A
000011	Y	N	5171B	5171B11
00000C	Y	Y	–	–
000001	N	N	12300	123001
000009	Y	Y	–	–
000010	Y	N	3141F	3141F10
000003	Y	N	23A21	23A213

• VA = 00000E

Found in TLB, and the valid bit is set, so TLB hit.

The dirty bit is also set, so the contents have to be written to memory.

PPN = 756AC

PA = PPN + offset = 756AC + E = 756ACE

 

• VA = 000016

Found in TLB, and valid bit is set, so TLB hit.

The dirty bit is not set.

PPN = 7390E

PA = PPN + offset = 7390E + 16 = 7390E16

 

• VA = 000009

Found in TLB, and the valid bit is not set, so TLB miss.

The dirty bit is not set.

In the main memory, the resident bit is 0. That means, it is not present in the main memory. Hence it is a page fault.

 

• VA = 00000A

Found in TLB, and the valid bit is not set, so TLB miss.

The dirty bit is also not set.

In memory, the resident bit is set.

PPN = 0A521

PA = PPN + offset = 0A521 + A = 0A521A

 

• VA = 000003

Not found in TLB, so TLB miss.

Present in the main memory and the resident bit is set, so no page fault.

PPN = 23A21

PA = PPN + offset = 23A21 + 3 = 23A213

 

Also, read the Given below-defined UML class diagram.